1. Technical Field
The present invention relates to a semiconductor integrated circuit with an internal dual-port static random access memory (SRAM) in which two ports, provided for each memory cell in the SRAM, can be respectively switched between writing data and reading data and used.
2. Related Art
A multi-port SRAM that can simultaneously read-write access a plurality of addresses is known as one type of SRAM. The multi-port SRAM described in JP-A-10-222983, an example of related art, includes a plurality of memory cells from which data can be read and to which data can be written; a read bit line pair that is placed in parallel on both sides of the memory cells in an array direction; a write bit line pair that is placed in parallel outside of the read bit line pair; a read word line for memory cell selection provided in correspondence with the read bit line pair; and a write word line for memory cell selection provided in correspondence with the write line pair.
In the multi-port SRAM, the two bit lines composing the read bit line pair have an intersecting region in the middle. Thus, coupling noise due to the influence of coupling capacitance present between the read bit line pair and the write bit line pair is cancelled. This is advantageous in that error can be prevented when writing and reading simultaneously. At the same time, in accompaniment with the intersecting of the two bit lines, a write inverting circuit that inverts in advance the value of data to be written to a specified memory cell and a read inverting circuit that inverts in advance the value of data read from a specified memory cell must be newly added.
Therefore, in JP-A-2003-78036, another example of related art, a multi-port SRAM that can quickly and stably output data read from a memory cell without the addition of a new circuit is described. FIG. 7 is a block diagram of a configuration of the multi-port SRAM described in JP-A-2003-78036.
The multi-port SRAM shown in FIG. 7 includes: a write decoder 1 to which a write address is applied; a read decoder 2 to which a read address is applied; N number of memory cells MC1 to MCN that are arrayed in a row at predetermined intervals between the write decoder 1 and the read decoder 2; a sense amplifier 5 that reads data from a memory cell specified by the read address and outputs the data as read data; and a write driver 6 to which write data is applied that writes data to a memory cell specified by the write address.
The write decoder 1 decodes the applied write address and activates only one word line among an N number of write word lines WW1 to WWN. The read decoder 2 decodes the applied read address and activates only one word line among an N number of read word lines RW1 to RWN.
The memory cells MC1 to MCN are respectively connected to the write word lines WW1 to WWN that correspond with the output of the write decoder 1 and are also respectively connected to the read word lines RW1 to RWN that correspond with the output of the read decoder 1. Two complementary read bit lines RB and /RB for reading data from each memory cell are placed in parallel on both sides of the memory cells MC1 to MCN in the array direction, thus forming a read bit line pair.
The read bit lines RB and /RB forming the read bit line pair intersect almost in the center of the region in which the memory cells MC1 to MCN are arrayed. Each memory cell and the read bit line RB are connected via a connecting wire 3. Each memory cell and the read bit line /RB are connected via a connecting wire 4. The connecting wires 3 and the connecting wires 4 of the memory cells MC1 to MCN/2, which are the upper half of the N number of memory cells MC1 to MCN, intersect.
The read bit lines RB and /RB are connected to a sense amplifier 5. The sense amplifier 5 amplifies a differential signal outputted from a memory cell specified by the read address and outputs a logic-level signal (read data).
Two complementary write bit lines WB and /WB for writing data to the memory cells MC1 to MCN are placed in parallel on both sides of the read bit lines RB and /RB, thus forming a write bit line pair. Each memory cell and the write bit line WB are connected via a connecting wire 7. Each memory cell and the write bit line /WB are connected via a connecting wire 8.
The write bit lines WB and /WB are connected to a write driver 6. The write driver 6 writes data to a memory cell specified by the write address by outputting a differential signal to the memory cell based on the write data.
In this way, the read bit lines RB and /RB intersect halfway and are switched left and right, and in correspondence, the connecting wires 3 and the connecting wires 4 intersect. Thus, data read from a memory cell can be output quickly and stably without the addition of a new circuit.
However, in the multi-port SRAM, the capacities placed on the bit lines are generally unbalanced between the write bit line pair composing a first port and the read bit line pair composing a second port. This is not a problem when one port is used exclusively for writing and the other port is used exclusively for reading. However, when this configuration is applied to a dual-port SRAM in which each port is respectively switched between writing data and reading data and used, this a problem in that the operating speeds between the two ports differ.
JP-A-10-222983 (page 1 and FIG. 1) and JP-A-2003-78036 (pages 3, 5 to 6, and FIG. 1) are examples of related art.